Tutorials

Large Language Models (LLMs) are entering every stage of electronic system development, and digital design was the first beneficiary. Frontier models now pass roughly 90% of standard register-transfer level (RTL) generation benchmarks, an agentic system has designed a complete RISC-V core from a 219-word specification, and electronic design automation (EDA) vendors are shipping agentic assistants. Analog and mixed-signal design tells a different story. A recent three-tier evaluation of two frontier models on ten fundamental analog circuits found excellent reasoning, mixed implementation and catastrophic simulator syntax, with at best three of ten netlists compiling on the first run. This asymmetry defines the current frontier of AI-assisted chip design.

This tutorial presents a comprehensive picture of LLM-based circuit design on both sides of that divide, and introduces the closed-loop design agent as the remedy for the analog gap. In the beginning, the landscape of LLM-assisted chip design is surveyed. The three-tier evaluation framework is then presented as the one-shot baseline. The core of the tutorial is dedicated to closed-loop agentic workflows, in which the model proposes a circuit, a deterministic layer repairs the netlist, an open-source simulator measures it, and the model revises the design from the measured feedback. New results on an open-source 180 nm foundry process are presented, showing which failures the loop recovers tier by tier and testing the model's causal claims against the simulator, including a live demonstration of the design agent. Participants will gain a practical, evidence-based methodology for applying design agents to their own circuits.

Motivation and Relevance

Microelectronics is experiencing its third great boom, and this time artificial intelligence is both the driver and the customer. Numerous fields such as automotive, telecommunications, biomedical devices and data centers depend on chips whose complexity keeps growing while the pool of experienced designers does not. LLMs represent a paradigm shift in how engineers interact with specifications, design data and simulation environments. In digital design the progress is measurable and fast. A 2026 IEEE Access review of thirty-one published efforts reports that frontier models reach up to 89.7% on the VerilogEval benchmark and 96.1% on RTLLM when a lightweight reflection loop is added, and an agentic system recently produced VerCore, the first complete RISC-V CPU core designed autonomously by AI agents, verified in simulation at 1.48 GHz. Commercial agentic tools are entering production EDA flows.

Yet despite this momentum, analog and mixed-signal design remains the hardest target for automation and the domain where the talent shortage is felt most sharply. Analog knowledge is largely tacit, the feedback is numeric rather than textual, and a single syntax mistake silently invalidates an otherwise sound design. The speaker's three-tier evaluation of Claude Opus 4.1 and ChatGPT-5 on ten fundamental circuits, published at ETECOM 2025, quantified this precisely: strong analytical reasoning at the top, systematic biasing errors in the middle, and a catastrophic failure of simulator syntax at the bottom, where one model compiled zero of ten netlists even after cleanup. For design teams the consequence is a knowledge gap. It is presently unclear what these tools can be trusted with, what a feedback loop can recover, and which failures are fundamental. This uncertainty leads to misplaced expectations in both directions, from blanket rejection to uncritical adoption.

This tutorial addresses that knowledge gap with measured evidence. It builds directly on the speaker's published three-tier baseline (ETECOM 2025) and on his new closed-loop study, in which an un-augmented LLM agent iterates against the open-source ngspice simulator on the open GlobalFoundries 180 nm process, supported by a deterministic netlist repair layer and a simulator-grounded audit of the model's own reasoning. The complete workflow runs on open tools and public repositories, and hence every result shown in the tutorial can be reproduced by the participants without commercial licenses. The topic sits at the intersection of design automation, analog and mixed-signal circuits and engineering education, all central themes of the ICM community, and it addresses a question that every design group and every engineering classroom currently faces.

Tutorial Content

The tutorial is organized in five parts. The durations include short transitions and add up to a three-hour session.

Part 1: The Landscape of LLMs in Chip Design (35 min)

In the beginning an overview of LLM-assisted chip design is given, establishing how language models represent circuit knowledge and why chip design is a demanding target for them. The current research directions are then classified for both the digital and the analog domain, separating augmented approaches, namely retrieval, design databases and fine-tuning, from un-augmented baselines that rely on the model alone.

Topics: LLM fundamentals for circuit designers, in-context learning, agents and tools, taxonomy of current approaches, the analog/digital asymmetry

Part 2: The One-Shot Baseline (35 min)

The three-tier evaluation framework is presented, separating design reasoning, implementation competency and syntax proficiency. Results of Claude Opus 4.1 and ChatGPT-5 on ten fundamental analog circuits in an open 180 nm process are discussed in detail, including the sophistication paradox in which advanced testbenches are undermined by elementary syntax errors. The revived strength of equation- based design methods is examined, since it carries direct implications for analog design education.

Topics: three-tier framework, benchmark circuits, tier-by-tier results, failure taxonomy, implications for design methodology and education

Part 3: Closing the Loop with Design Agents (50 min)

The core of the tutorial is dedicated to the closed-loop design agent. The anatomy of the loop is presented step by step: the specification, the proposed circuit, a deterministic netlist repair layer, simulation, measurement, evaluation against the specification, diagnosis and revision. Deterministic repair is contrasted with the common practice of asking the model to regenerate on error. The recoverability of failures is then decomposed tier by tier, separating what iterative feedback recovers from what remains knowledge-bound. To close, a reasoning-validity audit is introduced in which the model's stated causal claims are tested against the simulator, so that evidence-driven design is separated from fortunate search. The session includes a live demonstration in which an open-source agent designs an operational transconductance amplifier to a gain, bandwidth and phase-margin specification on the open 180 nm process.

Topics: agent anatomy, deterministic netlist repair, iterative feedback, tier-wise recoverability, reasoning- validity audit, live demonstration

Part 4: The View from Digital Design (30 min)

The digital domain is then examined as the reference point. The state of RTL generation is summarized, followed by the VerCore case study, a complete RISC-V core produced by an agentic system from a 219- word specification in twelve hours. Commercial agentic EDA tools and their intended use are reviewed, together with the recurring digital failure modes. Since digital loops close more easily thanks to executable testbenches and reference models, the ingredients that analog design can import are identified explicitly.

Topics: RTL generation benchmarks, reflection loops, the VerCore case study, agentic EDA tools, recurring failure modes, lessons for mixed-signal teams

Part 5: Hybrid Workflows, Adoption and Outlook (30 min)

Finally, a practical adoption playbook is presented for design teams and educators: where the tools can be trusted, which outputs must be verified, and how agent reasoning should be logged and audited. Open problems are stated plainly, including layout, parasitics, process corners and silicon validation. The session concludes with the open repositories and an open discussion.

Topics: hybrid human-agent workflows, verification discipline, open problems, resources and repositories, discussion

Learning Outcomes

After completing this tutorial, participants will be able to:

• Explain how LLMs represent circuit design knowledge and where the analog/digital capability asymmetry originates.
• Apply the three-tier framework (reasoning, implementation, syntax) to evaluate any model on their own circuits.
• Describe the anatomy of a closed-loop design agent and the role of the deterministic netlist repair layer.
• Distinguish failures that iterative feedback recovers from failures that are knowledge-bound.
• Audit the causal reasoning of a design agent against simulation instead of taking its explanations on faith.
• Reproduce the complete workflow with open-source tools and public repositories, without commercial licenses.

Keywords:

Large Language Models, design agents, analog circuit design, mixed-signal design, RTL generation, EDA, SPICE, open-source PDK

SRAM-based in-memory computing (IMC) improves the energy efficiency of matrix–vector multiplication by performing multiply–accumulate operations within the memory array, minimizing data movement in conventional accelerators. However, in analog and mixed-signal IMC macros, analog-to-digital converters (ADCs) often dominate peripheral area and energy while limiting throughput and computational accuracy. This tutorial presents a systematic approach to ADC design for SRAM-based IMC, connecting array-level computing requirements to converter architectures and circuit-level implementation. It examines how charge-, current-, voltage-, and time-domain computing schemes, array dimensions, input and weight precision, and partial-sum statistics determine ADC resolution, dynamic range, and throughput. Flash, sense-amplifier-based, successive-approximation-register (SAR), sigma-delta, and time-domain converters are compared in terms of energy, area, speed, effective resolution, and suitability for highly parallel, column-constrained IMC macros. Key circuit challenges, including comparator noise and offset, capacitor mismatch, thermal noise, and calibration, are discussed alongside cross-layer trade-offs involving resolution, column sharing, adaptive quantization, and Quantization or ADC-aware training. Emerging ADC-less and hybrid analog–digital approaches are also explored. Published silicon results are used to benchmark converter-level metrics against macro-level energy efficiency and computational accuracy, highlighting how technology scaling, array size, and workload precision influence optimal design choices. The tutorial provides circuit designers and AI hardware researchers with a practical framework for co-optimizing ADCs and SRAM-based IMC architectures for energy-efficient AI acceleration.

The rapid growth of wireless connectivity and increasing congestion in the sub-6 GHz spectrum have created strong demand for reconfigurable receivers that can support multiple frequency bands while maintaining high tolerance to adjacent-channel interferers. Conventional radios address this using multiple narrowband front ends, each optimized for a specific band, an approach that increases hardware complexity, silicon area, and power consumption. Reconfigurable receiver architectures offer an attractive alternative by enabling a single RF front end to support multiple wireless standards.

Among available techniques, N-path filters (NPF) have emerged as a powerful solution because they realize frequency-selective filtering that is programmable simply by adjusting the switching frequency. However, NPF performance is limited by switch losses, local oscillator power consumption, reciprocal mixing, and insufficient out-of-band rejection. Embedding N-path filtering within low-noise transconductance amplifier (LNTA)-based receivers improves linearity and frequency agility, but conventional second-order filtering often provides inadequate rejection of strong nearby interferers.

This tutorial will introduce staggered N-path filtering, combining multiple NPFs with offset center frequencies to synthesize a higher-order filter, as a technique for achieving fourth-order channel selectivity in frequency-reconfigurable receiver front ends. Using the presenters' recent IEEE Transactions on Microwave Theory and Techniques (TMTT) publication as the primary case study, the tutorial will provide both the theoretical foundation and the practical circuit design insight needed to build next-generation, interferer-tolerant, frequency-reconfigurable RF receivers.

Tutorial Outline

• NPF Fundamentals and Limitations - operating principles of N-path filtering; sources of switch loss, LO power consumption, reciprocal mixing, and out-of-band rejection limits
• Staggered N-Path Theory - principles of higher-order filtering via frequency-offset staggering; design methodology for selecting frequency offsets and filter parameters to achieve target bandwidth and in-band ripple
• Circuit Implementation - techniques for realizing fourth-order channel selectivity within an LNA-based receiver front end
• Design Trade-offs - noise, linearity, switch resistance, and out-of-band rejection considerations
• Case Study - walkthrough of the TMTT design, measured results, and lessons learned

Audience

RF/analog IC designers, graduate students, and researchers working on reconfigurable receivers, software- defined radio front ends, or interference-tolerant RF systems. A basic understanding of receiver architectures and mixer/filter concepts is helpful but not required.

Tactile sensing system is required widely for soft robotics, prosthetics, and wearable health devices. Large scale production of capacitive pressure sensors become expensive due to the need for cleanroom lithography. In this tutorial, we present an approach for designing low-cost and flexible sensor system. A step-by-step guide to building and characterizing flexible piezo- capacitive tactile sensor using screen printing, a graphene-nanoplatelet and carbon-nanotube nanocomposite ink, an elastomer dielectric, along with integrated chips is provided. The tutorial presents the need for learning chips to be integrated to sensor system to address the challenges of non-linearity and variability.

It is proposed that neuromorphic learning chips can be a cost and computationally efficient approach to build sensor systems. By the end of this tutorial, attendees will possess a complete, reproducible workflow, including a bill of materials tailored for typical laboratory budgets, the readout firmware, a plotting recipe for producing publication-quality figures, and a comprehen- sive characterization checklist.

Tutorial Outline

Part 1: Background and Fundamentals

• Part1—Fabrication(25min). Nanocompositeinkandtherationaleforahybridgraphene/nanotube filler; screen printing onto a flexible substrate, mask geometry, and the multi-coat protocol; cast- ing and laminating the elastomer dielectric with no cleanroom or vacuum step.
• Part 2 — RC Readout (25 min). The charge–discharge method and the RC time con- stant; microcontroller/neuromorphic chip implementation and conversion of a time-constant change into a measured voltage; firmware tracing, and how it exposes the mixed piezoresistive– piezocapacitive nature of the device.
• Part 3 — Characterisation Done Right (30 min). A set-level protocol distinguishing pre- cision from reproducibility under ISO 5725; honest reporting of sensitivity, linearity, hysteresis, and detection limit.
• Wrap-up and Q&A (10 min).

Learning Outcomes

After this tutorial, attendees will be able to: (i) fabricate a printed capacitive sensor without cleanroom access; (ii) implement and correctly interpret a microcontroller RC readout and on- chip learning circuits; and (iii) characterise a sensor to a standard that withstands peer review.

Target Audience and Prerequisites

Graduate students and early-career researchers in microelectronics, circuits and systems, mate- rials, or biomedical engineering. Prerequisites: basic circuit theory and undergraduate physics. No prior printed-electronics experience is assumed.

The growing deployment of electronic systems in aerospace, defense, healthcare, and Internet of Things (IoT) applications has made hardware security a critical design requirement. Conventional software-based security mechanisms are often inadequate against physical attacks, reverse engineering, and side-channel analysis, motivating the adoption of hardware security primitives. Among these, Physically Unclonable Functions (PUFs) have emerged as an effective solution by exploiting inherent manufacturing process variations to generate unique, device-specific signatures.

This tutorial, “PUF-Based Hardware Security: Architectures, Attacks, and Countermeasures,” provides a comprehensive overview of PUFs and related hardware security techniques. It introduces the fundamentals of hardware security primitives and explains the operating principles of weak and strong PUFs. Major PUF architectures, including SRAM, Ring Oscillator (RO), Arbiter, and latch-based PUFs, are discussed with emphasis on their design principles, advantages, limitations, and implementation challenges. The tutorial also covers PUF modeling and key evaluation metrics such as uniqueness, reliability, randomness, uniformity, bit error rate (BER), and key error rate (KER).

Beyond PUFs, the tutorial discusses hardware metering, IC authentication, logic locking, and hardware obfuscation for supply-chain security and intellectual property protection. Practical applications, including secure key generation, device authentication, embedded systems, biomedical electronics, and space applications, are presented. The tutorial further examines machine learning-based modeling attacks and electromagnetic (EM) side-channel attacks targeting PUFs, followed by countermeasures to enhance resilience through architectural improvements and leakage reduction techniques. Designed for researchers, engineers, and graduate students, the tutorial provides both theoretical foundations and practical insights into designing secure and trustworthy hardware systems.

The continuous scaling of semiconductor devices has driven the technology industry to develop faster, smaller, and more efficient transistors. As technology nodes have miniaturized, traditional planar transistors have struggled with short-channel effects, leakage currents, and power consumption issues. FinFETs emerged as a revolutionary solution to address these challenges. Despite the advantages, below the sub-22nm node, FinFETs possess challenges, such as parasitic capacitance and resistance, fin depopulation, and variability in fin height and width. These limitations have prompted the development of new transistor architectures, such as stacked transistors, including Nanosheet FET, Forksheet FET, and CFET (Complementary FET), with improved power, performance, area, and cost (PPAC). These architectures comprise vertically stacked multiple channels/sheets, reducing the device's overall footprint while maintaining or improving performance. Stacked devices offer enhanced flexibility in gate control and channel width optimization and improve power efficiency since multiple channels are integrated without increasing the device's lateral area, enabling more transistors to be packed into a smaller space. The integrity of the device (e.g., stacked transistor) raises several call-up challenges related to the electrical and thermal reliability. The vertical stacking of channels in these devices creates complex electrostatic interactions between sheets, leading to research on performance optimization. Further, owing to the compact stacked design, the channels/sheets are prone to self-heating problems, as the heat accumulates in the wrapped channel by low-thermal-conductivity material. Further, the heat generated in one sheet may couple to another, affecting the device's normal operation. Therefore, the mutual coupling of electrical and thermal parameters is essentially considered for such stacked transistors. Electrical coupling, in one way or another, can increase parasitic capacitance and interfere with channel signal transmission, leading to degraded device performance. On the other hand, the mutual electrical and thermal coupling exacerbates self-heating issues, negatively affecting both performance and reliability. Furthermore, the additional internal and external process variations, such as interface traps, random dopant fluctuation (RDF), gate metal grain granularities (MGG), line- edge roughness (LER), NBTI, etc., raise reliability concerns, which play a critical role, leading to premature device degradation and failure. Ensuring the long-term reliability of stacked transistors requires careful consideration of these failure mechanisms and the development of mitigation strategies, which can help predict device aging. In particular, as transistor architectures become more complex, accurate capacitive and resistive behavior modeling becomes critical for device circuit co- design. For FinFETs, modeling the gate capacitance and resistive paths is relatively straightforward. However, stacked transistor architectures introduce new complexities due to the vertical arrangement of channels and gates. These vertical stacks create capacitive coupling between the layers, which impacts device performance, particularly in high-frequency applications. Nanosheet transistors offer improved high-frequency performance due to reduced parasitic capacitance and improved electrostatic control. Accurate modeling of Nanosheet transistors in high- frequency and their circuit implications are critical for leveraging their potential in modern technology nodes to ensure signal integrity. Thus, designing a robust model (quasi-static or non-quasi-static), addressing the SOEs, and evaluating the reliability challenges requires proper attention in agreeing to accept such stacked transistors as an integrated industrial fit. In addition, the radiation effects, particularly in advanced nodes where devices are more sensitive to external perturbations, also impact the resistive paths within the transistor. High-energy particles can induce transient faults or cause permanent resistance changes, necessitating robust radiation-aware resistance models for mission-critical applications.

This tutorial session will provide a detailed overview of the evolution from FinFETs to advanced stacked architectures, emphasizing their implications for high-frequency performance, modeling complexity, and reliability challenges. Through the lens of both traditional and TCAD approaches, we aim to explore the design considerations and circuit-level impacts that will define the next era of semiconductor innovation.